1. Technical Field
The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a technology of controlling a read operation of a nonvolatile memory cell using a channel resistance of the memory cell which changes with a polarization state of a nano-scaled ferroelectric material.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and preserves data even after the power is turned off.
A FeRAM having a structure similar to a DRAM includes capacitors made of a ferroelectric substance, so that it utilizes the high residual polarization characteristic of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
A unit cell of a conventional nonvolatile FeRAM device includes a switching element and a nonvolatile ferroelectric capacitor. The switching element performs a switching operation depending on a state of a word line to connect a nonvolatile ferroelectric capacitor to a bit line or disconnect the nonvolatile ferroelectric capacitor from the bit line. The nonvolatile ferroelectric capacitor is connected between a plate line and a terminal of the switching element. Here, the switching element of the conventional FeRAM is an NMOS transistor whose switching operation is controlled by a gate control signal.
FIG. 1 is a cross-sectional view of a unit cell of a conventional nonvolatile ferroelectric memory device.
A conventional 1-T (One-Transistor) FET (Field Effect Transistor) cell includes an n-type drain 2 and an n-type source 3 which are formed in a p-type substrate 1. Also, the cell includes an insulation oxide 4, a ferroelectric layer 5, and a word line 6 which are sequentially formed on a channel region between the drain 2 and the source 3.
The above-described conventional nonvolatile FeRAM device reads and writes data by using a channel resistance of the memory cell which changes with a polarization state of the ferroelectric layer 5.
Specifically, the channel region has a high resistance when the polarity of the ferroelectric layer 5 induces positive charges to the channel, and a low resistance when the polarity of the ferroelectric layer 5 induces negative charges to the channel.
However, in the conventional nonvolatile FeRAM device, when the cell is scaled down, a data retention characteristic is degraded, especially if a nonvolatile ferroelectric memory cell has been fabricated on a nanometer scale. For example, in a read mode, a read voltage may appear at adjacent cells, which can generate crosstalk noise, thereby destroying data stored in these cells. In a write mode, a write voltage may appear at an unselected cell so that data stored in unselected cells are destroyed. As a result, it is difficult to perform a random access operation.